Typically, many identical integrated circuits are constructed on a single wafer of semiconductor material, such as silicon or gallium arsenide. The portion of the wafer occupied by a single one of the integrated circuits is called a die. After fabrication of the integrated circuits is completed, a series of tests is performed on the wafer in which a set of functional tests of each die is performed at a probe test station. The test data collected for each die is used in subsequent assembly/packaging steps to ensure that only properly functioning die are packaged as integrated circuit chips.
Following the probe test, the individual dies are separated from one another and each properly functioning die is encapsulated in a package to form a packaged die that is commonly referred to as an integrated circuit. Subsequently, a series of testing operations may be performed for each of the integrated circuits.
While semiconductor device manufacturing processes continue to improve, manufacturing induced defects can still occur. Such defects can arise from uncontrollable process variations or particulate contamination. For the most part, these defects are not catastrophic, and only give rise to a limited number of nonfunctional memory cells within a large memory array. To prevent such relatively small defects from destroying a memory device, it is common practice to employ “redundant” memory cells.
System on a Chip (SoC) devices typically include one or more memory arrays, each of which includes large number of memory cells arranged in rows and columns. The memory cells are accessed by the application of an address, which results in the selection of a row and a column (or a group of columns). Commonly, memory cells within the same row are coupled to a word line, while memory cells within the same column are coupled to a bit line (or bit line pair). In response to a row address, a given word line will be activated, coupling a row of memory cells to their respective bit line. In response to a column address, selected bit lines are coupled to an input/output (I/O) bus, allowing data to be read from, or written to, the selected memory cells.
Redundant memory cells are extra memory cells that can be used to replace defective memory cells. In this manner, a device can essentially repair itself by accessing the redundant memory cells instead of the defective memory cells. A redundancy scheme can include row-wise redundancy and/or column-wise redundancy. In the case of row-wise redundancy, one or more extra rows of memory cells are created within the array. In the event an applied memory address corresponds to a row having a defective memory cell, one of the extra rows of memory cells is accessed in place of the row containing the defective memory cell. In the case of column-wise redundancy, the extra columns of memory cells are created within the array. In a memory access operation, the bit line associated with the extra column is coupled to an I/O bus in place of the bit line of a column having defective memory cells.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.